Semiconductor transistors typically include source/drain regions that are spaced apart from each other in a semiconductor substrate, as well as a gate pattern that is disposed over the channel region that separates the spaced apart source/drain regions. The source/drain regions may be formed as lightly doped drain (LDD) regions in order to minimize a phenomena known as hot carrier effect.
FIG. 1 is a cross-sectional diagram that illustrates a method for fabricating a conventional semiconductor transistor that has an LDD structure.
As shown in FIG. 1, the transistor includes a gate pattern 5 that is formed on a semiconductor substrate 1. The gate pattern includes a gate oxide film 2, a gate electrode 3 and a capping pattern 4 that are sequentially stacked. After the gate pattern is formed, impurity ions may be injected at a relatively low dose into the semiconductor substrate 1 using the gate pattern 5 as a mask, thereby forming first and second low-concentration impurity-doped regions 6 in the semiconductor substrate 1.
After the region 6 is formed, spacers 7 may be formed on sidewalls of the gate pattern 5. Thereafter a relatively high dose of impurity ions may be injected into the semiconductor substrate 1 using the gate pattern 5 and the spacers 7 as an implantation mask to thereby form first and second high-concentration impurity-doped regions 8 in the semiconductor substrate 1. The first low and high-concentration impurity-doped regions 6, 8 form a first source/drain region 9 and the second low and high-concentration impurity-doped regions 6, 8 form a second source/drain region 9. The low and high-concentration impurity-doped regions 6, 8 may be thermally treated to activate the impurities after the ion implantation process.
In conventional transistors such as the transistor depicted in FIG. 1, the line width of the gate pattern 5 is typically made very small in order to increase the integration level of the semiconductor device in which the transistor is provided. As the line width is reduced, a phenomena known as “short channel effect” may occur that may deteriorate the characteristics of the transistor. Although the impact of the short channel effect may be reduced by forming the transistor to have an LDD architecture in which the shallow, low-concentration impurity-doped region 6 is provided on each end of the channel region, the LDD architecture may not completely solve the short channel effect problem because the shallowly implanted impurities in the low-concentration impurity-doped region 6 may diffuse during subsequent thermal processes.